The world of electronics is an ever-shrinking world. The physical space needed and/or allocated to implement a given function is getting smaller and smaller. The use of dual-sided, multi-layer printed circuit boards with miniature surface mount technology (SMT) components and custom application-specific integrated circuits (ASICs) installed thereon to form small, compact, printed circuit assemblies is now common. The spacing between the pins of components becomes smaller as the designs are made to fit into smaller physical configurations. The physical spacing, such as pin spacing and wire trace spacing, is further reduced when the assembly is intended to be portable, such as a modem designed to support the Personal Computer Memory Card International Association (PCMCIA) standard.
In the context of such a crowded and densely populated printed circuit assembly, it is often difficult to determine if an electronic device or component has been installed correctly. More particularly stated, it is often difficult to determine whether there are any shorts between the wire traces or nodes of the PCB, the pins or leads of the installed device or component, and other wire traces, circuit nodes, pins or leads (hereinafter "nodes"). Historically, such determinations have been made by one or a combination of three testing methodologies: "Bed of nails" testing, boundary scan testing and capacitive testing.
"Bed of Nails" Testing
One method of testing a printed circuit assembly involves use of a "bed of nails" test fixture with a conventional in-circuit tester, such as an HP 3070 Board Tester manufactured and distributed by the Hewlett-Packard Company of Palo Alto, Calif. The bed of nails test fixture provides a number of contact probes for accessing points on the printed circuit assembly. There must be contact between the probes of the fixture and a device on the printed circuit assembly or signal paths on the printed circuit assembly (typically via a conventional test point access node) for the test method to work. The method is often called a "bed of nails" testing method because the probes are typically sharp metal contact probes configured so that the printed circuit assembly can be placed on the "bed of nails" and tested. In this manner, the probes touch or access various parts of the device or the signal paths on the printed circuit assembly (via the test point access nodes on the printed circuit assembly) and thereby allow measurements to be made on the device.
Typically, the in-circuit tester measures the resistance between all possible pairs of probes. Measurements from the probes are then compared to "correct" values to determine whether there are any shorts. However, the appropriate signal path must be in physical contact with the test probes for this testing method to work. Densely populated printed circuit assemblies often have inaccessible signal paths, such as wire traces beneath multiple layers on the printed circuit board assembly, thereby hampering the use of such a "bed of nails" test fixture. Therefore, "bed of nails" test fixtures are often ineffective when attempting to test a densely populated printed circuit assembly. In particular, those nodes without probe access cannot be tested for shorts by this method.
Boundary Scan
Those skilled in the art will be familiar with Boundary Scan, which is another test method for determining proper connectivity. Boundary Scan (illustrated in FIG. 1 as prior art and also known as IEEE 1149.1 or Joint Test Action Group (JTAG)) is a specialized non-contact test method for testing the board-level interconnections among devices on a printed circuit assembly. More particularly, Boundary Scan is a special form of conventional scan path testing that is implemented around every input/output pin of a device in order to provide controllability and observability of the input/output pin values during testing.
Referring now to FIG. 1, the Boundary Scan method generally uses a set of four pins 110a, 110b for each device 115a, 115b. These pins allow an in-circuit tester (not shown) to gain access to all of the pins on the device 115a, 115b. The in-circuit tester (not shown) typically sends commands to a boundary scan port 105a within the device 115a in order to read or control the input pins and the output pins on the device 115a. Those skilled in the art will realize that while the boundary scan port 105a is typically implemented within the circuitry of the device 115a, the boundary scan port 105 a may also be implemented as a separate circuit. FIG. 1 merely shows the boundary scan ports 105a, 105b implemented within the circuitry of the devices 115a, 115b in order to avoid confusion.
Boundary Scan is most advantageous when a printed circuit assembly 100 has several interconnected devices 115a, 115b which implement it. This is advantageous because it is then possible to use, for example, port 105a, to generate an output on one pin 120a and read it from a connected pin 120b on another device 115b via, for example, port 105b, without having physical access to either of the pins 120a, 120b or the signal path 125 between the pins 120a, 120b. This is particularly advantageous because the same pins and signal paths which are used for Boundary Scan testing are later used to create the normal function of the circuit during normal operation. The term "normal operation" is used to describe the operation of the completed circuit assembly by the consumer or end user in the manner intended by the designer.
The digital version of Boundary Scan is more formally defined by the Institute of Electrical and Electronics Engineers, Inc. (IEEE) and the published IEEE standard 1149.1 (1990). The analog version of Boundary Scan is more currently being defined as IEEE 1149.4 (1997). Additional information regarding Boundary Scan is available by referring to the published IEEE 1149.1 standard, which is available from IEEE, Inc., New York, N.Y. Furthermore, while still not in a final form, information regarding the preliminary IEEE 1149.4 Boundary Scan standard is also available from IEEE, Inc., New York, N.Y.
While Boundary Scan testing allows testing of interconnected devices without accessing the pins of the interconnected devices, one skilled in the art will appreciate that such testing is not useful in all situations. For example, Boundary Scan testing is less useful where there is only one device implementing Boundary Scan and that device is surrounded by devices that do not implement or support Boundary Scan testing. In such a situation, it is often necessary to access many of the pins or signal paths on the printed circuit assembly with a probe. Thus, it may still be difficult to test the integrity of connections of a device on a populated printed circuit assembly using Boundary Scan.
Additional limitations of Boundary Scan are evident with reference to the faulty circuits depicted in FIGS. 4 and 5. If pin 401.1 is tested by Boundary Scan, then the short can be detected if either of pins 401.1 or 401.2 are an output pin (or a bidirectional pin) and the other is an input pin (or a bidirectional pin). However, the Boundary Scan configuration cannot detect the short if both pins are output pins or both pins are input pins, and if IC 402 and 403 do not support Boundary Scan. Referring now to FIG. 5, if pin 501.1 is tested by a Boundary Scan system, then the short can be detected if either of the pins 501.1 and 501.2 is an output pin (or a bidirectional pin) and the other is an input pin (or a bidirectional pin). However, the Boundary Scan configuration cannot detect the short if both pins 501.1 or 501.2 are output pins or both pins are input pins, and if IC 502 does not support Boundary Scan.
An additional limitation of Boundary Scan is that it is good at detecting open connections between devices which support Boundary Scan, but it is less effective at detecting shorts. In particular, it may often fail to detect shorts of the type later shown in FIG. 6, where the short joins together two devices which support Boundary Scan with two devices which do not.
For instance, FIG. 6 illustrates yet another type of short between nodes on a PCB. In the diagram IC 601, IC 602, IC 603, and IC 604 each has a capacitive sensor (not shown) positioned proximately near them so as to detect any test signal coupled to a node associated with that IC, as will be discussed subsequently in reference to capacitive testing. There is a short between IC 601 pin one (601.1) and IC 603 pin 1 (603.1), and 603.1 cannot be accessed by a test probe. In prior systems, this short would not be detected by a bed-of-nails tester, because there is no probe access to pin 603.1. With prior methods, this short might not be detected.
Capacitive Testing
Another testing method for testing the integrity of a device's connections is capacitive testing. An example of such capacitive testing is described in U.S. Pat. No. 5,254,953 (hereinafter "the '953 patent") entitled "Identification of Pin-Open Faults by Capacitively Coupling Through the Integrated Circuit Package" and assigned to the Hewlett-Packard Company of Palo Alto, Calif. In the '953 patent, a system is described for determining whether pins of a device are properly soldered to a printed circuit board assembly. FIG. 2 illustrates such a prior art system.
Referring now to FIG. 2, a printed circuit assembly 200 has an integrated circuit device 205 mounted to a printed circuit board 210. A capacitive sensor 215 is positioned over the device 205 while a test probe 220 contacts a pin under test 225 via a pad 226 and a connection 222 between the pin 225 and the pad 226.
In a capacitive testing process disclosed in the '953 patent, the test probe 220 typically injects an alternating current (AC) test signal (such as a 10 kHz signal at 0.2 volts) into the pad 226 connected to the pin under test 225. The capacitive sensor 215 then detects this test signal via the capacitive coupling between the pin 225 and the bottom of the capacitive sensor 215 and converts the AC signal to an intermediate signal called a detection signal. The value of the detection signal is proportional to the detected amplitude of the AC signal. In this manner, the value of the detection signal from the capacitive sensor 215 may be compared to a threshold value to determine characteristics about the detected AC signal (such as the strength of the AC signal). If the pin 222 between the test pad 226 and pin under test 225 is open, the value of the detection signal will be much smaller than anticipated. An in-circuit tester (not shown) connected to the capacitive sensor 215 then indicates that the printed circuit assembly 200 has failed the test and declares that the pin under test 225 is open.
While the capacitive testing process described in the '953 patent allows testing to detect open pins on populated printed circuit boards, a test probe is still required to provide the test signal. Moreover, test probe access to the pin under test must still be available for capacitive testing as described in the '953 patent to work. Such a capacitive testing process would be ineffective in a circuit assembly where test probe access to the pin under test is not available, such as a densely populated circuit assembly where the pin spacing and wire trace spacing are extremely small.
It is well known that capacitive testing can detect shorts to non-probed pins under certain conditions. Referring, for instance, to the faulty circuit depicted, for illustrative purposes, in FIG. 4, capacitive testing can detect the short between a probed pin of IC 401 and a non-probed pin of IC 401 under two conditions. First, if the non-probed pin is floating, and thus does not decrease the signal level of the AC test signal driven into the probed pin, then the short may be detected because there is now twice as much capacitance coupling the test signal to the capacitive sensor. This results in an unusually strong detection signal, which may be detected as a short. Second, if the non-probed pin is strongly driven to a fixed level by its internal driver or by other circuitry to which it is connected, and thus decreases the signal level of the AC test signal driven into the pin, then the short may be detected because of the decreased signal coupled to the capacitive sensor. However, the defect would probably be diagnosed as an open pin rather than as a short.
More specifically, if pin 401.1 is tested by means of a test signal applied to it by an external signal source, the short may be detected by the capacitive sensor at IC 401 because of the unusually large or small detection signal. However, in the prior art the capacitive sensor cannot identify the other shorted node, and may not detect the short at all due to the fairly small (typically 2 to 3 dB) difference in signal level between a non-shorted and a shorted node. Because the difference in signal level is close to the expected variability in measurements of good PCBs it is difficult to set detection limits which reliably detect shorts without simultaneously rejecting good PCBs. Also because of the small difference in signal level, the algorithms or other measuring means used to measure the signal level at 401 must be fairly accurate. In the prior art the capacitive sensor at IC 403 is not enabled during the test of IC 401, so it can neither detect the short nor provide additional information which could be used to identify the shorted nodes.
An inherent difficulty with this test method is that the decreased signal level due to the driven pin 401.2 may be masked by the increased capacitance, making detection of this fault unreliable. Also, capacitive testing cannot determine which nodes are shorted--it can only determine that the short involves one pin located under the capacitive sensor (the pin currently under test), and the other node(s) being one (or more) of the non-probed nodes on this PCB.
Yet another limitation of capacitive testing is evident with reference to the faulty circuit depicted in FIG. 5. More particularly, FIG. 5 is a diagram illustrating another type of short between nodes on a PCB. In FIG. 5 IC 501 and IC 502 each have a capacitive sensor (not shown) positioned proximate to them so as to detect any test signal coupled to a node associated with that IC. There is a short between IC 501 pin one (501.1) and IC 501 pin 2 (501.2), and neither 501.1 nor 501.2 can be accessed by a test probe.
Without probe access to 501.1 and 501.2, these pins may not be tested by an external signal source.
If IC 501 is used as an onboard controllable signal source for testing pins 501.1, 501.2, 502.1, and 502.2, then the short may be detected by the increased signal level at the capacitive sensors positioned proximately near IC 501 and IC 502. However, because of the variability in output signal level of the onboard controllable signal source from one PCB to another and the desire to set detection limits which do not cause a false detection of shorts, the tester may fail to detect the short. Similarly, the short depicted in FIG. 6 would not be detected by capacitive sensors, whether in conjunction with an onboard or external signal source, because the sensors at IC 603 and IC 604 would not be enabled or examined while testing IC 601 and IC 602.
In summary, for detecting shorts between devices mounted on a populated printed circuit assembly, there is a need for a system that: (1) improves the capacitive testing method to allow detection of shorts between pins without physically probing the pins (2) allows testing without probing a signal path connected to the pins (3) reduces the required number of test point access nodes on the printed circuit assembly (4) allows detection of shorts where there is only one device on the printed circuit assembly implementing Boundary Scan or where a Boundary Scan device is surrounded by other devices that do not implement or support Boundary Scan testing; (5) allows the cooperative use of both external and onboard controllable signal sources for maximum circuit coverage; and (7) allows the shorted nodes to be identified without probe access.